1. Field of the Invention
This invention relates generally to application specific integrated circuits (ASICs) and in particular to a single cell structure used for both boundary scan testing and built-in self-testing of ASIC logic during manufacturing testing.
2. Description of the Related Art
In an application specific integrated circuit (ASIC) there are two general problems encountered in the manufacturing testing process. The first problem is that the ASIC logic itself is defective and the second is that the circuitry used to get signals into the ASIC logic and out of the ASIC logic is defective. Consequently, test logic is built into an ASIC that is used only in the manufacturing process to verify the operability of the ASIC. After the manufacturing process is complete, the ASIC test circuitry is passive and is no longer required or used.
Typically, the ASIC built-in test logic includes a built-in self-test (BIST) capability as well as a boundary scan capability. For a boundary scan capability, boundary scan register cells (BSRCs) are placed between all the ASIC pins, that are used either as data input or data output pins, and the ASIC logic. Here, "data input pins" refers to the pins that provide input signals to the ASIC logic and "data output pins" refers to the pins that receive output signals from the ASIC logic.
The BRSCs may be used for a variety of manufacturing tests because the BRSCs provide direct control of all the data input pins and all the data output pins independent of the ASIC logic. The IEEE has evolved IEEE 1149.1 standard for boundary scan.
Built-in self-test (BIST) refers to any test circuitry which permits the ASIC to test itself. The advantages of BIST are that no special test patterns or test equipment are required and the ASIC can be tested independent of its environment.
There are many types of BIST. One type of BIST uses a pseudo-random number generator (PRNG) to drive each input line to the ASIC logic. Each PRNG creates a non-repeating, predictable, pseudo-random pattern on the input line that the PRNG drives. As the ASIC logic is clocked, these patterns propagate through the ASIC logic to the output lines of the ASIC, where a pseudo-random number signature analyzer (PRSA) is located. The PRSA is similar to a PRNG in that for any finite set of input signals to the PRSA, the PRSA creates a "signature" bit-pattern. While the signal pattern presented to the PRSA changes with each clock tick, the PRSA signature is based on the current and past input signals and thus represents a "history" of all previous patterns. By connecting the PRSA to an ASIC output line, a "history" of all previous ASIC output signals is generated. If any ASIC output line, at any clock cycle, has the wrong value, the signature generated by the PRSA differs from the signature generated by a PRSA in a known good device. By checking the signature of an ASIC under test against a signature from a known good ASIC tested under the same conditions, the functionality of the ASIC under test is determined.
ASIC 100 (FIG. 1) includes both built-in self-test capability and boundary scan capability for ASIC logic 110. The boundary scan capability is provided by input boundary scan register cells (BSRCs) 103-1 to 103-4, output boundary scan register cells 104-1 to 104-4, and test logic 120. The built-in self-test capability is provided by pseudo-random number generator cells 105-1 to 105-4, pseudo-random number signature analyzer cells 106-1 to 106-4, and test logic 120. ASIC 100 has four input pins 101-1 to 101-4 and four output pins 102-1 to 102-4.
As illustrated in FIG. 1, the configuration of the input and output boundary scan register cells 103-1 to 103-4 and 104-1 to 104-4 and pseudo-random number generator and signature analyzer cells 105-1 to 105-4 and 106-1 to 106-4 for each input pin and output pin is the same. Thus, the following description for input pin 101-2 and output pin 102-2 is applicable for any of the other input pins and output pins, respectively, of ASIC 100.
Input pin 101-2 drives an input boundary scan register cell 103-2 which in turn provides an input signal to pseudo-random number generator cell 105-2 that in turn drives an input line of ASIC logic 110. Similarly, a signal on an output line of ASIC logic 110 drives pseudo-random number signature analyzer cell 106-2. The output signal of cell 106-2 drives output boundary scan cell 104-2, which in turn drives output pin 102-2.
Test logic 120 drives control lines for the boundary scan cells, both input and output, and the pseudo-random number generator and signature analyzer cells. Typically, the built-in self-test and the boundary scan capability form an on-chip monitor architecture that conforms to IEEE 1149.1 standard. This standard requires that ASIC 100 have four additional pins, which are test data in signal pin TDI, test data out signal pin TDO, test mode select signal pin TMS, and test clock pin TCK. Test reset pin TRST* is an optional pin, but when test reset pin TRST* is used, the standard defines its use. In addition, most ASICs include, as illustrated for ASIC 100, an asynchronous ASIC reset pin RST and an asynchronous three-state output pin TRIST for use in normal operation of ASIC logic. However, for manufacturing tests, test logic 120 also typically includes a means for generating signals on lines TRISTATE and RESET to ASIC logic 110.
The built-in test circuitry may also include an internal scan capability in addition to the boundary scan and built-in self-test capabilities. For an internal scan of ASIC logic 110, input signals from pin TDI are passed through test logic 120 to ASIC logic 110 and the resulting signals from ASIC logic 110 are passed through test logic 120 to pin TDO. Test logic 120 generates a signal on line SS to configure flip-flops in ASIC logic 110 for the internal scan and in addition provides a clock signal on line CLK for the scan.
A typical structure for an input boundary scan register cell 203 and a typical structure for an output boundary scan register cell 304 are illustrated in FIGS. 2 and 3, respectively. Input boundary scan register cells 103-1 to 103-4 are identical and are represented by cell 203 (FIG. 2). Output boundary scan register cells 104-1 to 104-4 are also identical and are represented by cell 304 (FIG. 3). Moreover, the basic structure of cell 203 and cell 304 is the same. The only difference in cells 203 and 304 is the source of the input signal for the cell and the use of the output signal from the cell.
Each cell 203, 304 includes two two-to-one multiplexers 211, 214 and 311, 314 and two D-type flip-flops 212, 213 and 312, 313. Test logic 120 drives five control lines which are used by cells 203, 304. If the signal on control line MODE is active, the input signal to cell 203, 304 is not simply passed through the cell. Rather, multiplexer 214, 314 passes the signal generated by D-type flip-flops 212, 213 and 312, 313 to the cell output line.
In normal operation of ASIC 100, cells 203 and 304 add two two-to-one multiplexers signal propagation time delays between the input and output pins of ASIC 100. This time delay is in addition to the time delay of ASIC logic 110.
In addition to the time delay, cells 203 and 304 increase the gate count of ASIC 100. The size of a logic section in ASIC 100 is measured by the number of "equivalent gates" required to build the logic section. Herein, the number of equivalent gates is the number of the two input NAND gates required to duplicate the function of the logic section. Using an equivalent gate count, different designs can be compared on an equal basis. Table 1 gives the equivalent gate count for one BSRC, either an input or an output BSRC.
TABLE 1 ______________________________________ # Equivalent Total # Gate Type Gates # in Cell Equivalent Gates ______________________________________ 2 Input MUX 3 2 6 D Flip-Flop 8 2 16 with Clear ______________________________________ Total equivalent gates in cell 22 ______________________________________
Thus, in view of Table 1, the boundary scan register cells require an additional 44 equivalent gates for each input pin-output pin pair. Alternatively, in general EQU BSRC Gate Count=(# Input Pins)*22+(# Output Pins)*22
A typical structure for a pseudo-random number generator cell 405 and a typical structure for a pseudo-random number signature analyzer cell 506 are illustrated in FIGS. 4 and 5 respectively. Pseudo-random number generator cell 405 (FIG. 4) represents pseudo-random number generator cells 105-1 to 105-4 and pseudo-random number signature analyzer cell 506 (FIG. 5) represents pseudo-random number signature analyzer cells 106-1 to 106-4. Each cell 405, 506 includes an exclusive OR gate, 416, 516, a D-type flip-flop, 417, 517, and a two-to-one multiplexer 418, 518. Each cell 405, 506 receives three control signals from test logic 120. If signal TEST.sub.-- MODE is active, the pseudo-random number built-in self-test feature is enabled.
One difference in cells 405 and 506 is the source of the input signal and the use of output signal of the cell. The other difference is the number of input lines to the exclusive OR gate.
In normal operation of ASIC 100, cells 405 and 506 add two two-to-one multiplexer signal propagation time delays between the input and output pins of ASIC 100. This time delay is in addition to the time delay of ASIC logic 110 and in addition to the time delay introduced by the boundary scan register cells. In addition to the time delay, cells 405 and 506 also increase the gate count of ASIC 100. Tables 2 and 3 give the gate count for one pseudo-random number generator cell and one pseudo-random number signature analyzer cell, respectively.
TABLE 2 ______________________________________ # Equivalent Total # Gate Type Gates # in Cell Equivalent Gates ______________________________________ 2 Input MUX 3 1 3 D Flip-Flop 8 1 8 with Clear 2 input XOR 4 1 4 ______________________________________ Total equivalent gates in cell 15 ______________________________________
TABLE 3 ______________________________________ # Equivalent Total # Gate Type Gates # in Cell Equivalent Gates ______________________________________ 2 Input MUX 3 1 3 D Flip-Flop 8 1 8 with Clear 3 input XOR 12 1 12 ______________________________________ Total equivalent gates in cell 23 ______________________________________
Thus, in view of Tables 2 and 3, the built-in self test capability introduces an additional 38 gates for each input pin-output pin pair. Alternatively, in general, EQU BIST PRN Gate Count=(# Input Pins)*15+(# Output Pins)*23.
For ASIC 100, the total equivalent gate count for the boundary scan cells and built-in self-test cells is: EQU GATE COUNT=(# Input Pins)*37+(# Output Pins)*45.
Boundary scan and BIST, as discussed above, add both logic gates to ASIC 100 and a propagation delay for signals as the signals travel through the additional test circuitry. Both of these effects are detrimental to the ASIC performance and cost.
The physical size and cost of ASIC 100 is proportional to the number of gates in ASIC 100. Thus, adding test circuitry directly increases the physical size and component cost of ASIC 100. Frequently, design and cost restraints force some test circuitry to be omitted due to the additional size/cost requirements. This reduces the testability of ASIC 100 and increases the manufacturing cost of the product on a whole, as the overall ASIC testability is reduced.
Any test circuitry placed in series with ASIC logic 110 between an input pin and an output pin adds signal propagation delay time as the signals are routed through the additional test circuitry. This occurs even in normal ASIC operation. Unfortunately, as ASICs are used in higher speed systems, the time delay which the ASIC can tolerate and still operate properly diminishes. Only minimal additional time delays can be tolerated. In some cases, the time delays incurred by including both boundary scan and BIST, as discussed above, are too great and either the boundary scan or BIST functionality is omitted. This reduces the testability of the ASIC and increases the manufacturing cost of the product as a whole, because the overall ASIC testability is reduced.